For example, in order to manufacture a printed board, manufacturing data is output from a physical design Computer Aided Design (CAD) system for the printed board. The manufacturing data includes Gerber data used for creating an artwork film. The Gerber data expresses a graphic to be filled in, such as a plane pattern or the like, using the locus (a line whose width is the diameter of a circle) of a circle having a certain radius. When a portion occurs that is hard to express using the Gerber data, there is a discrepancy between the portion and the data from the physical design CAD system. Therefore, in the physical design CAD system for the printed board, a plane pattern is filled in using a line having a certain width (the diameter of a circle used for expressing the Gerber data), and a portion hard to fill in (namely, a filling-in width violation portion) is detected and displayed to a designer as an error, or is automatically corrected.
As one of related techniques for detecting the filling-in width violation portion, there has been a method in which the shortest distance between the sides of of polygon shapes configuring plane patterns is obtained as illustrated by arrows in FIG. 1 and a filling-in width violation portion is detected by comparing the distance with a filling-in width. In this technique, since the shortest distance between the sides of the plane patterns is obtained, if the number of the corners of the plane patterns of processing targets increases, the number of sides also increases and the number of the combinations of sides increases. Therefore, a processing time is lengthened. Specifically, in an undesirable case, since a time is taken that is proportional to the square of the number of corners, an operation calculating distances between sides turns out to be performed one trillion times in a plane pattern the number of corners of which exceeds one million. In addition, not only the filling-in width violation portion is detected, but also processing for rounding off a corner whose angle is less than or equal to a certain angle is performed at the same time, in order to deal with electro-magnetic compatibility (EMC) or the like. In addition, filling-in violation indicates a filling-in width violation, an acceptable angle violation, or both thereof.
As another related technique, there has been a method in which a filling-in width violation portion is detected by performing an image processing operation. In this technique, data is treated as two-dimensional mesh data. Therefore, when graphic data such as a plane pattern or the like is held as a one-dimensional corner array, since processing for converting data is performed, an extra processing load rests. Examples of documents disclosing the above-mentioned techniques include Japanese Laid-open Patent Publication No. 05-242197, Japanese Laid-open Patent Publication No. 06-28425, Japanese Laid-open Patent Publication No. 2005-321846, Japanese Laid-open Patent Publication No. 07-56978, and Tsukizoe Akira, Kozawa Tokinori, Sakemi Junya, Miura Chihei, and Ishii Tatsuki, “A pattern logical operation method simultaneously processing logical operation and intersection point calculation for VLSI mask data (A concurrent pattern operation algorithm for VLSI mask data)”, IEICE Transactions on Electronics, '86/6 Vol. J69-D No. 6.